1. Field of the Invention
The present invention relates to a metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, and a method of manufacture thereof.
2. Description of Related Art
A SOI-structure MOS field-effect transistor can be driven at a lower power consumption and a higher speed than an ordinary MOS field-effect transistor.
A schematic view of an example of a conventional SOI-structure MOS field-effect transistor is shown in FIG. 32. A buried oxide film 1100 formed of a silicon oxide layer is formed on a silicon substrate 1000. A source region 1200 and a drain region 1300 are provided in mutually separate locations on the buried oxide film 1100. A body region 1400 is formed on the buried oxide film 1100, between the source region 1200 and the drain region 1300. A gate electrode 1500 is formed on the body region 1400 with a gate insulation film therebetween.
The body region 1400 of the MOS field-effect transistor of FIG. 32 is in a floating state. Thus carriers generated by impact ionization tend to accumulate in the body region 1400. If carriers accumulate, the potential of the body region 1400 changes. This phenomenon is called the substrate floating effect. This causes various problems in the MOS field-effect transistor, such as the kink phenomenon and the parasitic bipolar effect.
There is a SOI-structure MOS field-effect transistor which can suppress this substrate floating effect. A schematic view of such a MOS field-effect transistor is shown in FIG. 33. This MOS field-effect transistor is called a dynamic threshold-voltage MOSFET (DTMOS). It differs from the MOS field-effect transistor shown in FIG. 32 in that the body region 1400 and the gate electrode 1500 are placed in electrical contact. This connection makes it possible for excess carriers that have accumulated within the body region 1400 to be drawn out of the body region 1400. This stabilizes the potential of the body region, making it possible to prevent the occurrence of the substrate floating effect. In addition, any rise in the gate voltage leads to a rise in the body potential, so it is possible that the ON current will increase and also the OFF current will decrease.
However, a DTMOS has another problem in that it can only be used in practice under low gate voltage conditions of a gate voltage on the order of 1 V or less. Specifically, a voltage that is applied to the body region in a DTMOS is of the same magnitude as the voltage applied to the gate electrode thereof. The application of a voltage to the body region causes a forward bias voltage to be applied to the PN junction formed by the body region and the source region. Since the breakdown voltage in the forward direction of a PN junction is usually on the order of 0.7 V, any increase in the gate voltage beyond that point will cause a large current to flow between the body region and the source region. This current will make it impossible to achieve the lower power consumption that is the objective of a SOI structure. Such a current would cause errors in the operation of the circuitry comprising the SOI structure. In addition, since a small forward-direction current flows between the body region and the source region, even when the DTMOS is used at a gate voltage of less than 0.7 V, this impedes any reduction in the power consumption.
An objective of the present invention is to provide a metal insulator semiconductor (MIS) field-effect transistor of silicon-on-insulator (SOI) structure and a method of manufacture thereof that make it possible to achieve a lower power consumption, even during use under conditions of a comparatively high gate voltage.
According to a first aspect of the present invention, there is provided a metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, comprising a source region, a drain region, a body region, a gate electrode, and a PN junction portion, wherein the body region is interposed between the source region and the drain region;
wherein the body region is electrically connected to the gate electrode by the PN junction portion; and
wherein the PN junction portion is disposed in such a manner that when a voltage is applied to the gate electrode, a reverse voltage is applied to the PN junction portion.
The present invention having the above described configuration achieves the effects discussed below. In accordance with the present invention, the PN junction portion is disposed between the gate electrode and the body region, in a path that travels from the gate electrode, through the body region, and into the source region. The PN junction portion is disposed in such a manner that when a voltage is applied to the gate electrode, a reverse voltage is applied to the PN junction portion. Thus, when a voltage is applied to the gate electrode, a reverse voltage is applied to the PN junction portion, which ensures that only a small current on the order of the reverse leakage current of the PN junction flows along that path. This makes it possible to restrain the power consumption of the SOI-structure MIS field-effect transistor, even when it is used under conditions of a comparatively high gate voltage.
Note that this current suppression effect can be achieved even when a resistor is disposed between the gate electrode and the body region in the path from the gate electrode, through the body region, and into the source region. However, the PN junction portion to which a reverse voltage is applied, as in the present invention, makes it possible to achieve an effect that is similar to the current suppression effect of a resistor though an area of the PN junction is smaller than that of the resistor.
Note that an ordinary diode or a Zener diode could be used as the type of the PN junction portion in accordance with the present invention. The material of the PN junction portion of the present invention could be polysilicon or silicon single crystal, by way of example. The types and materials cited above are merely given as examples, and it should be obvious that these could be selected as appropriate from consideration of factors such as the voltage range of the device and the device dimensions.
The PN junction portion in accordance with the present invention could be formed at two different positions, by way of example.
With one position, the MIS field-effect transistor may further comprise an extended portion extending from an end portion of the gate electrode and the PN junction portion may be included in the extended portion.
With the second position, the MIS field-effect transistor may be formed on a silicon-on-insulator (SOI) substrate, and the PN junction portion may be formed within a silicon single crystal layer of the SOI substrate.
The MIS field-effect transistor of the present invention that is provided with the above described extended portion could be in either of two states, by way of example.
In the first state, the MIS field-effect transistor of the SOI structure maybe formed on a silicon-on-insulator (SOI) substrate and further comprise an interlayer dielectric and a connecting layer,
wherein the interlayer dielectric is formed to cover the extended portion and a silicon single crystal layer of the SOI substrate;
wherein the interlayer dielectric has a hole through which is exposed part of the extended portion and the silicon single crystal layer of the SOI substrate; and
wherein the connecting layer is formed in the hole to electrically connect the extended portion to the silicon single crystal layer of the SOI substrate.
In the second state, the MIS field-effect transistor of the SOI structure may be formed on a silicon-on-insulator (SOI) substrate and further comprise an insulating layer,
wherein the insulating layer is positioned between the extended portion and a silicon single crystal layer of the SOI substrate;
wherein the insulating layer has a hole through which is exposed part of the silicon single crystal layer of the SOI substrate; and
wherein the extended portion is electrically connected to the silicon single crystal layer of the SOI substrate through the hole.
The transistor of the present invention having a structure in which the PN junction portion is formed in the silicon single crystal layer of the SOI substrate could be in the following state, by way of example.
The MIS field-effect transistor of the SOI structure may further comprise an interlayer dielectric and a wiring layer,
wherein the interlayer dielectric is formed to cover the silicon single crystal layer of the SOI substrate;
wherein the interlayer dielectric has a first hole through which is exposed part of the silicon single crystal layer of the SOI substrate, and a second hole through which is exposed part of the gate electrode;
wherein the wiring layer is formed on the interlayer dielectric; and
wherein the wiring layer is electrically connected to the silicon single crystal layer of the SOI substrate by the first hole, and is also electrically connected to the gate electrode by the second hole.
According to a second aspect of the present invention, there is provided a method of manufacturing a metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, the method comprising the steps of:
(a) forming a body region in a silicon-on-insulator (SOI) substrate;
(b) forming a gate electrode and also forming an extended portion that is positioned so as to extend from an end portion of the gate electrode;
(c) using the gate electrode and the extended portion as a mask for the implantation of impurities of a first conductivity type into the SOI substrate,
wherein a source region and a drain region of the first conductivity type are formed in such a manner that the body region is interposed between the source region and the drain region; and
wherein a first portion of the first conductivity type is formed in the extended portion;
(d) forming a second portion of a second conductivity type connected to the first portion, by implanting impurities of the second conductivity type into the extended portion;
(e) forming an interlayer dielectric to cover the silicon single crystal layer of the SOI substrate;
(f) forming a hole in the interlayer dielectric through which is exposed part of the extended portion and the silicon single crystal layer of the SOI substrate; and
(g) electrically connecting the extended portion to the silicon single crystal layer of the SOI substrate by forming a connecting layer within the hole.
According to a third aspect of the present invention, there is provided a method of manufacturing a metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, the method comprising the steps of:
(a) forming a body region in a silicon-on-insulator (SOI) substrate;
(b) forming an insulating layer including a gate insulating film on the body region;
(c) forming a hole in the insulating layer through which is exposed part of a silicon single crystal layer of the SOI substrate; and
(d) forming a gate electrode and an extended portion on the insulating layer,
wherein the extended portion is positioned to extend from an end portion of the gate electrode, and is electrically connected to the silicon single crystal layer of the SOI substrate by the hole;
(e) using the gate electrode and the extended portion as a mask for the implantation of impurities of a first conductivity type into the SOI substrate;
wherein a source region and a drain region of the first conductivity type are formed in such a manner that the body region is interposed between the source region and the drain region; and
wherein a first portion of the first conductivity type is formed in the extended portion;
(f) forming a second portion of a second conductivity type connected to the first portion, by implanting impurities of the second conductivity type into the extended portion.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, the method comprising the steps of:
(a) forming a body region in a silicon-on-insulator (SOI) substrate;
(b) forming a gate electrode; and
(c) using the gate electrode as a mask for the implantation of impurities of a first conductivity type into the SOI substrate,
wherein a source region and a drain region of the first conductivity type are formed in such a manner that the body region is interposed between the source region and the drain region; and
wherein a first portion of a first conductivity type is formed in a silicon single crystal layer of the SOI substrate;
(d) forming a second portion of a second conductivity type by implanting impurities of the second conductivity type into the silicon single crystal layer of the SOI substrate,
wherein the second portion is connected to the first portion, and is positioned between the first portion and the body region;
(e) forming an interlayer dielectric in such a manner as to cover the silicon single crystal layer of the SOI substrate;
(f) forming a first hole in the interlayer dielectric to expose part of the silicon single crystal layer of the SOI substrate and forming a second hole in the interlayer dielectric to expose part of the gate electrode; and
(g) forming a wiring layer on the interlayer dielectric,
wherein the wiring layer is electrically connected to the silicon single crystal layer of the SOI substrate by the first hole; and
wherein the wiring layer is also electrically connected to the gate electrode by the second hole.